1. Technical Field
Apparatuses consistent with exemplary embodiments relate to a flip-flop with a zero-delay bypass multiplexer, and more particularly, to a flip-flop with a zero-delay bypass multiplexer which may achieve a design for test (DFT) coverage not incurring an additional delay.
2. Description of the Related Art
In a related art, a master-slave flip-flop configuration is typically used to manipulate a clock input which is fed into at least one memory circuit. For example, the manipulated clock input may be a divided clock or a stretched clock.
However, in the related art, a DFT coverage for the memory circuit may be lost if the clock input is manipulated by the master-slave flip-flop. Therefore, the memory circuit disposed downstream of the related art master-slave flip-flop configuration requires a regular clock input for DFT testing.
In order to address the problem of requiring a regular clock input for DFT of the memory circuit, the related art adds a downstream multiplexer to allow a regular clock to be utilized for DFT testing of the memory circuit. FIG. 1 shows an example of a conventional master-slave flip-flop circuit 10, which provides an output CKm to a conventional bypass multiplexer. The conventional bypass multiplexer is located downstream of the conventional master-slave flip-flop circuit 10, and provides a CKOut signal based on a CK signal, a bypass signal BYP, and the output from the conventional master-slave flip-flop circuit 10. However, adding the downstream multiplexer increases a time delay. The time delay may cause a hold time violation. In this scenario, a hold time violation occurs when the memory circuit receives the regular clock input at a time which violates the timing constraints of the memory circuit. Moreover, the hold time violation may require an additional hold buffer to account for the time delay, such that the regular clock is input within the timing constraints of the memory circuit. Thus, when the downstream multiplexer is added as in the related art, power consumption, timing delay, and circuit size may increase. Additional power consumption, timing delay, and circuit size occur as a result of the downstream multiplexer and the additional hold buffers. Thus, an improved configuration for DFT is needed which does not require increased power consumption, timing delay, and circuit size.